Verifying the true jitter performance of clocks in high-speed digital designs
Verifying the true jitter performance of clocks in high-speed digital designsAs the data rates in high-speed digital designs increase, the limits for overall system jitter become tighter. This especially applies to the various components of the clock tree, where the jitter limits for reference clocks, clock buffers and jitter attenuators are even tighter. Due to […]
Outphasing, Envelope & Doherty transmitter test & measurement
Outphasing, Envelope & Doherty transmitter test & measurementMeeting the efficiency challenge of RF front ends (RFFE) is increasingly difficult at higher operating frequencies and bandwidths, such as those proposed for 5G. There is a group of transmitter RFFE architectures whose signal output is constructed from two, or more, efficiently generated components. The architecture of their […]
Optimize Doherty power amplifiers
Optimize Doherty power amplifiersDoherty designs achieve high efficiency, greater linearity and increased output power. Get deep insight into your design with a dual-path, precisely synchronized source driving the Doherty amplifier and improve your yield. The admin of this site has disabled the download button for this page.
Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs
Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designsIncreasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture, consisting of a jitter-attenuator and a frequency-synthesizer stage. Due to their […]