Siemens has expanded the early design verification functionalities of its Calibre platform for IC physical verification.
Siemens Digital Industries Software has launched a range of expanded electronic design automation (EDA) early design verification functionalities for its Calibre platform for integrated circuit (IC) physical verification. Engineered to help IC design teams and companies get to tapeout faster, these new capabilities can help IC designers “shift left” their physical and circuit verification tasks by moving the identification, analysis, and resolution of complex IC and system-on-chip (SoC) physical verification issues into earlier stages of the design and verification flow.
Identification and resolution of issues earlier in the design cycle can not only help compress the overall verification cycle, but also provide more time and opportunity to improve final design quality. By providing tuned check support for these early-stage analysis, verification and optimization strategies using qualified signoff requirements, Siemens enables design companies to streamline their design processes, improve designer productivity and reduce time-to-market.
“Extending technology leadership in the EDA space requires constant improvement driven by a deep understanding of the specific challenges customers face in their daily work,” said Michael Buehler-Garcia, vice president of Product Management for Calibre Design Solutions, Siemens EDA. “The introduction of these new early design verification capabilities underscores Siemens‘ ongoing commitment to providing customers with the very latest technologies they need to quickly deliver world-class silicon products to market regardless as to the stage of the design they are working in.”
Among the new functionalities for the Calibre platform are:
The Calibre nmPlatform tool suite is also differentiated in the EDA industry with its integration across all major IC design and layout implementation tools. This seamless integration enables design teams to easily run Calibre tools at the intellectual property (IP), block/macro, and full-chip levels, all from their custom design or place and route (P&R) design cockpit. In addition, the Calibre plaform’s unique viewing and debug capability can result in speed enhancements at all design stages.