Start-up delivers ASICs using RISC-V

Article By : Rick Merritt

So far open-source silicon has failed to gain traction, and it’s still early days for RISC-V, the latest and broadest effort to date.

A start-up aims to help a broader set of engineers roll out their own silicon using its customisable open-source systems-on-chips. SiFive will publish specifications for an SoC-based on an embedded Linux processor core and one using a microcontroller core both based on work of the RISC-V Foundation.

“We want to give more people access to custom silicon,” said Yunsup Lee, co-founder and chief technology officer of SiFive and one of the inventors of the royalty-free RISC-V instruction set architecture at the University of California at Berkeley.

The work comes on the heels of a record year of semiconductor mergers, in part driven by the need to defray the increasing complexity and cost of designing leading-edge chips. “We think the industry is going the wrong way,” said Jack Kang, SiFive’s vice president of product and business development, pointing to the start-up’s 28nm and 180nm platforms.

So far open-source silicon has failed to gain traction, and it’s still early days for RISC-V, the latest and broadest effort to date. The RISC-V group is rounding out fundamental parts of its specifications in areas such as debugging, and software support is still embryonic but interest is steadily growing since it was formally announced in 2014.

As many as 250 people from 63 companies are expected to attend the fourth RISC-V workshop this week, including board members from Microsemi, Nvidia and Western Digital. Members of the non-profit jumped to 40 companies from 16 in January and include Google, IBM, Microsoft and Oracle.

[SiFive 01]
__Figure 1:__ *SiFive founders Yunsup Lee (left) and Andrew Waterman with their Berkeley graduate adviser Krste Asanovic (centre). (Image: SiFive)*

At the event, SiFive will let attendees try out their RISC-V SoCs implemented on a Microsemi FPGA board. The company hopes to land initial customers in the next several months.

Ted Speers, head of product architecture and planning for Microsemi’s SoC group, and a RISC-V Foundation board member, praised SiFive in a press statement. SiFive’s “agile methodology enabled [them] to deliver a complete RISC-V sub-system and tool-chain targeting our secure, low power SmartFusion-2 SoC FPGA platform on a very aggressive schedule,” he said.

“It's quite believable that open source hardware can decrease the cost of new design starts by enabling more design re-use and lower IP costs,” said David Kanter, a processor analyst with The Linley Group who also blogs on his own website.

On the other hand, SiFive is essentially testing a new theory that there is a significant class of technical people barred by traditional costs but interested in specifying new processor instructions and blocks to differentiate products, Kanter added. Overall, “open source has proven to be a pretty powerful force in the software world, but it's unclear how that will map into the hardware world,” he said.

Start-up sketches out platform specs

SiFive’s Freedom U500 is a multicore RISC-V SoC running at up to 1.6GHz in TSMC 28nm process. It supports PCIe 3.0, USB 3.0, Gigabit Ethernet, and DDR3/DDR4 peripherals and targets machine learning, storage and networking systems.

The E300 targets the Internet of Things and wearables with a single-core MCU built in an 180nm process, optimised for size and power. It uses RISC-V compressed instructions that can reduce code size as much as 30%.

The start-up’s cores will use a cache coherent interconnect called TileLink, defined by a Berkeley graduate student. The company is preparing TileLink for release as an open spec and writing converters to mate it with popular interconnects such as ARM’s Amba.

“People avoid custom silicon because of the cost, they get an MCU that’s not exactly what they want and make compromises,” said Kang of SiFive

Engineers could tap SiFive, for example, to define a unique security block or custom security instructions for an SoC. “Storage customers talks about custom instructions for bit manipulation so they can use one not 10 instructions for 10x speed up,” Kang said.

Although the start-up is not disclosing costs, Kang suggested “a moderate Kickstarter campaign could now get custom silicon.”

One sore spot for SiFive and RISC-V as a whole is the nascent state of supporting tools and software.

Analyst Kanter pointed to the founders’ roots developing processor cores and blocks at Berkeley. “There is real potential in their tool chain… [but] their work to date has been academic, which means that many crucial product-level considerations may have been omitted (e.g., yield, binning, DFM, DFT),” he said.

Kang claims SiFive has three real-time OSes ported to its platforms, including FreeRTOS. The FreeBSD operating system has been ported to RISC-V.

Progress in Cambridge, potential in China

In general, analysts said the start-up and RISC-V in general hold disruptive promise, but they took a wait-and-see view of whether either will gain commercial traction.

“It is too early to determine if the solutions will be competitive from a product (performance and efficiency) or market (price and time-to-market) standpoint,” but the SiFive and RISC-V work “eventually could change the business models of the semiconductor industry,” said Jim McGregor, principal analyst at Tirias Research.

It's particularly hard to gauge the cost advantages given SiFive and existing licensors such as ARM don’t disclose specifics. “It is almost impossible to develop a chip today without having to pay royalty fees to someone and SiFive will still need other technologies to build SoCs for customers,” McGregor noted.

“China is the Wild West for sever chips…leveraging licensed ARM, x86, and Power architectures to chart their own course and break Intel's monopoly on the market,” McGregor said. “I wouldn't be surprised if the Chinese vendors are also taking a closer look at the RISC-V ISA for various applications,” he added.

Among other news at the RISC-V workshop this week, the University of Cambridge Computer Laboratory will report progress on its LowRiSC core. A “major added feature is support for trace debug—think along the lines of ARM's CoreSight or Intel Processor Trace,” said Alex Bradbury, a director of the LowRISC effort.

The lab also is taking part in Google’s Summer of Code project. It posted a blog on its work that incudes “porting the Arduino software library to the PULPino RISC-V implementation, porting the BSD-licensed Musl libc, and [doing] work on a secure trusted execution environment” for RISC-V, he added.

Separately, a group of interns in Cambridge “are working on adding video output and accelerated video decoding,” and posted a demo of their initial work.

Leave a comment