Synopsys Unveils RF Design Flow for TSMC N6RF Process

Article By : Synopsys Inc.

Synopsys' new RF design flow, developed with Ansys and Keysight for the TSMC N6RF process, boosts 5G SoC development productivity.

Addressing increasingly complex RFIC design requirements, Synopsys Inc. has launched a new RF design flow developed with Ansys and Keysight for the TSMC N6RF process, the most advanced RF CMOS technology that offers significant performance and power efficiency boosts. The flow helps mutual customers achieve power and performance optimizations for 5G chips while also accelerating design productivity for faster time-to-market.

“Our latest collaboration with Synopsys addresses the challenges of next-generation wireless systems, enabling designers to deliver greater connectivity, higher bandwidth, lower latency and better coverage for our increasingly connected world,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “With high-quality, tightly integrated solutions from Synopsys as well as Ansys and Keysight, the new TSMC RF Design Reference Flow for the TSMC N6RF process provides a modern, open approach that enhances productivity for developing these complex ICs.”

RFICs for wireless data transmission systems, such as transceivers and RF front-end components, are becoming more complex based on the demands of our connected world. These next-generation wireless systems are expected to deliver higher bandwidth, lower latency and better coverage across more connected devices. To ensure their RFICs can meet these requirements, designers must be able to accurately measure parameters such as RF performance, spectrum, wavelength and bandwidth.

The new RF design reference flow improves design turnaround time with industry-leading circuit simulation and layout productivity performance, as well as accurate electromagnetic (EM) modeling and electromigration/IR-drop (EMIR) analysis. The flow includes the Synopsys Custom Compiler design and layout product, Synopsys PrimeSim circuit simulation product, Synopsys StarRC parasitic extraction signoff product and Synopsys IC Validator physical verification product; Ansys VeloceRF inductive component and transmission line synthesis product, Ansys RaptorX and Ansys RaptorH, the advanced nanometer electromagnetic (EM) analysis products, and Ansys Totem-SC; and Keysight’s PathWave RFPro for EM simulation.

“To enable key differentiating advantages for 5G designs, Synopsys continues to deliver robust RF design solutions that integrate electromagnetic synthesis, extraction, design, layout, signoff technologies and simulation workflows,” said Aveek Sarkar, vice president of engineering at Synopsys. “Because of our deep collaboration with TSMC and strong relationships with Ansys and Keysight, our customers can now take advantage of the advanced features within the Synopsys Custom Design Family, using TSMC’s  advanced N6RF technology for 5G applications, to improve productivity and achieve silicon success.”

“RF design customers benefit significantly from the interoperability between Synopsys Custom Compiler and PathWave RFPro in the TSMC reference flow,” said Niels Fache, vice president and general manager of PathWave Software Solutions at Keysight Technologies. “Shifting electromagnetic co-simulation left in the design process enables RF circuit designers to optimize for the parasitic effects in advanced chips and multi-technology modules for 5G and WiFi 6/6E applications. This saves days and sometimes weeks in the simulation workflow, while reducing the risk of costly re-spins in the product development cycle. Our partnership with Synopsys and TSMC gives RF customers the design tools and advanced process technology they need to ensure high performance with first-pass success.”

“Ansys is excited to collaborate with Synopsys and TSMC on an advanced reference flow for RFIC designs,” said Yorgos Koutsoyannopoulos, vice president of research and development at Ansys. “Significant complexity driven by the growing need for 5G and 6G designs, along with advanced process effects at nanometer nodes, pose a big challenge to RFIC designers. Accurately modeling advanced process effects in EM and EMIR analyses is critical to creating first-pass silicon operating from DC to tens of GHz. Working seamlessly with the Synopsys Custom Complier platform, Ansys tools such as VeloceRF, RaptorX, Exalto and Totem-SC have the highest capacity to handle the most challenging designs as well as the ability to model all advanced process effects. They provide an intuitive and easy-to-use flow for the design, optimization and verification of RF design blocks.”

 

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