2017-06-26 - EE Times India

Buffer design qualifies for 650V on 200mm wafers

The GaN-on-Si device technology is Au-free and compatible with the wafer handling and contamination requirements for processing in a Si…

2017-06-16 - EE Times India

Arria 10 board achieves 40Gbps interoperability

The setup is composed of The Dini Group’s DNPCIE_80G_A10_LL board and Exostiv Labs’ Exostiv Dashboard for Intel FPGA.

2017-06-15 - EE Times India

Tiny OPNFV lab acts as data centre for NFV dev’t

The NFV PicoPod is a complete OPNFV Pharos pod, condensed to a cubic foot package and consists of six Marvell…

2017-05-02 - Brian Santo

Keeping up with rapidly evolving 5G

Part of the problem is that 5G is not one proposed standard, it’s a growing set of them.

2017-05-02 - EE Times India

FPGA design suite offers mixed language simulation

The Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator, which allows line by line verification of hardware description…

2017-04-28 - EE Times India

Hackers challenged to crack patented encryption

Contestants will have three weeks to hijack patented cryptography method Blurry Box and report their exploits to win ₹35.71 lakh…

2017-04-24 - EE Times India

Hyundai Mobis India centre to focus on future tech

The Hyderabad-based Mobis Technical Centre of India will be transformed into an R&D centre specialising in automotive software.

2017-04-20 - Rajan Bedi

How to select COTS components for space apps

The selection of a COTS part is as much about how a component is used as the individual device itself.

2017-04-17 - Upendra Somashekaraiah, Manish Sagarvanshi, Sarvang Sanghavi

Resistance scaling affects other design parameters

Applying resistance scaling can have side effects on other design parameters, like shorts, DRCs and density.

2017-04-17 - Upendra Somashekaraiah, Manish Sagarvanshi, Sarvang Sanghavi

Resistance scaling fixes PNR, signoff STA mismatch

Resistance scaling is a powerful tool for meeting timing demands, particularly when there is miscorrelation between PNR and signoff STA…