Efinix's Efinity RISC-V Embedded Software IDE simplifies the creation, management, and debug of projects running on the Efinix Sapphire RISC-V…
Tessolve is working to enable its first RISC-V based SOC reference design in early 2023 using Intel Pathfinder for RISC-V.
UST and KITVEN have jointly invested in Calligo Technologies for developing Posit-enabled RISC-V multicore processors.
With its upgraded membership, Ventana founder and CEO Balaji Baktha will be joining the RISC-V Board of Directors.
RISC-V International and CHIPS Alliance have formed a new OmniXtend working group which will focus on creating an open, cache…
The rise of the RISC-V open standard is more about innovation and freedom of choice than an ISA religious war...
Open source hardware is more complex, with multiple layers in the stack, meaning it’s not as simple as shipping software...
Demand for special purpose domain specific accelerators can benefit from using RISC-V vector extension with high-bandwidth memory system.
RISC-V represents a clean slate. It offers a fantastic opportunity to build a platform that’s fit for 21st century products...
Andes’ new processor cores enable scalability by delivering RVV instruction extension and new memory subsystem. The company claims to be…