The Cadence IP for GDDR6 is silicon proven on TSMC’s N5 process technology, exceeding Cadence's previous 16Gbps designs.
Cadence's Integrity 3D-IC platform has achieved certification for and met all reference design flow criteria for TSMC's 3DFabric offerings.
Synopsys' new RF design flow, developed with Ansys and Keysight for the TSMC N6RF process, boosts 5G SoC development productivity.
Mixel's MIPI C-PHY/D-PHY Combo IP is now available on TSMC’s N5 process.
The announcement marks the migration of NXP's S32 family of processors to increasingly advanced process nodes as automobiles continue to…
TSMC plans to continue making chips for Huawei even as other companies in the global semiconductor ecosystem are complying with…
The Taiwanese foundry is unexpectedly adding a node that provides significant performance gain without having to redesign
At its 30th anniversary celebration, TSMC hosted a forum of key customers including semiconductor CEOs and Apple chief operating officer…
Liang Mong-song, a former employee at TSMC who leaked process technology to Samsung several years ago, has joined China's SMIC…